library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------
entity abs_generator is
port(	a: in std_logic_vector (7 downto 0);
		b: in std_logic_vector (7 downto 0);
		absv: out std_logic_vector (7 downto 0));
end abs_generator;
----------------------------------------------------------------
architecture abs_generator of abs_generator is

begin
absv<=	(a-b) when (a>b) else
			(b-a) when (b>a) else
			"00000000" when (a=b) else
			"ZZZZZZZZ";

end abs_generator;