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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity comparator1 is
port (a : in bit_vector (3 downto 0);
		b : in bit_vector (3 downto 0);
		equal : out bit;
		greater : out bit;
		less :out bit);
end comparator1;

architecture comparator1 of comparator1 is

begin
compare: process(a,b)
begin
if (a=b) then
				equal <= '1';
				greater <= '0';
				less <= '0';
elsif (a>b) then
				equal <= '0';
				greater <= '1';
				less <= '0';
elsif (a<b) then
				equal <= '0';
				greater <= '0';
				less <= '1';
else	equal <= '0';
		greater <= '0';
		less <= '0';
end if;
end process compare;
end comparator1;