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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_unSIGNED.ALL;
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entity comparator2 is
port (a : in signed (3 downto 0);
		b : in signed (3 downto 0);
		equal : out std_logic;
		greater : out std_logic;
		less :out std_logic);
end comparator2;

architecture comparator2 of comparator2 is
signal temp : signed (3 downto 0);
begin
temp <= a-b;
compare: process(a,b,temp)
variable zer : signed (3 downto 0);
begin
zer := "0000";
if (temp = zer) then
				equal <= '1';
				greater <= '0';
				less <= '0';
elsif (temp(3)= '0') then
				equal <= '0';
				greater <= '1';
				less <= '0';
elsif (temp(3)= '1') then
				equal <= '0';
				greater <= '0';
				less <= '1';
else	equal <= '0';
		greater <= '0';
		less <= '0';
end if;
end process compare;
end comparator2;