library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity dual_comparator is
port(	a: in std_logic_vector (7 downto 0);
		b: in std_logic_vector (7 downto 0);
		mode : in std_logic;
		agtb : out std_logic);
end dual_comparator;

architecture dual_comparator of dual_comparator is
signal agb,sgnd,unsgnd: std_logic;
signal c: std_logic_vector (8 downto 0);
signal d: std_logic_vector (8 downto 0);
signal e: std_logic_vector (8 downto 0);


begin
d <= (a(7),a(7),a(6),a(5),a(4),a(3),a(2),a(1),a(0));
e <= (b(7),b(7),b(6),b(5),b(4),b(3),b(2),b(1),b(0));
c <= d-e;
agb<=(not(d(8))and e(8))or(not(c(8)));
unsgnd<=	'1' when (a>b) else
			'0';
sgnd<=	'0' when c="000000000" else
			'0' when c(8)='1' else
			agb;
agtb<=	unsgnd when mode='0' else
			sgnd when mode='1' else
			'Z';

end dual_comparator;