library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity priority_encoder2 is

port (r: in std_logic_vector (7 downto 0);
		c: in std_logic_vector (2 downto 0);
		code: out std_logic_vector (2 downto 0);
		active: out std_logic);
end priority_encoder2;
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architecture priority_encoder2 of priority_encoder2 is

begin
active <=	'0' when r="00000000" else
				'1';
			code <=	c when r(conv_integer(unsigned(c)))='1' else
			c-1 when r(conv_integer(c-1))='1' else
			c-2 when r(conv_integer(c-2))='1' else
			c-3 when r(conv_integer(c-3))='1' else
			c-4 when r(conv_integer(c-4))='1' else
			c-5 when r(conv_integer(c-5))='1' else
			c-6 when r(conv_integer(c-6))='1' else
			c-7 when r(conv_integer(c-7))='1' else
			"ZZZ";

end priority_encoder2;