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-- Company:
-- Engineer:		Dimitrios Porlidas
-- 
-- Create Date:	19:54:32 12/17/2015 
-- Design Name: 
-- Module Name:	main - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity main is
port (
			CLK: in STD_LOGIC;
			led: out std_logic_vector (7 downto 0)
		);
end main;

architecture Behavioral of main is
signal state : STD_LOGIC_VECTOR (26 downto 0);
begin
process (CLK)
begin
	if CLK='1' and CLK'event then
		state<=state+1;	 				
	end if;	 	
led<=state (26 downto 19);
end process;



end Behavioral;